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| Integrated Circuit Systems, Inc. ICS8302-01 LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT FEATURES * Complementary LVCMOS / LVTTL output * LVCMOS / LVTTL clock input accepts LVCMOS or LVTTL input levels * Maximum output frequency: 250MHz * Output skew: 165ps (maximum) * Part-to-part skew: 800ps (maximum) * Small 8 lead SOIC package saves board space * Full 3.3V or 3.3V core, 2.5V supply modes * 0C to 70C ambient operating temperature * Industrial temperature information available upon request GENERAL DESCRIPTION T h e I C S 8 3 0 2-01 i s a l o w s k e w, 1 - t o - 2 LVCMOS/LVTTL Fanout Buffer w/ComplemenHiPerClockSTM tary Output and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8302-01 has a single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels. The ICS8302-01 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for o u t p u t o p e r a t i n g s u p p l y m o d e s (V DDO). G u a r a n t e e d output and part-to-part skew characteristics make the I C S 8 3 0 2-01 i d e a l f o r clock distribution applications demanding well defined performance and repeatability. ,&6 BLOCK DIAGRAM Q CLK nQ PIN ASSIGNMENT VDDO VDD CLK GND 1 2 3 4 8 7 6 5 Q GND VDDO nQ ICS8302-01 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 8302AM-01 www.icst.com/products/hiperclocks.html 1 REV. A DECEMBER 10, 2002 Integrated Circuit Systems, Inc. ICS8302-01 LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT Type Power Power Input Power Output Output Pulldown Description Output supply pins. Core supply pin. LVCMOS / LVTTL clock input. Power supply ground. Complementary clock output. LVCMOS / LVTTL interface levels. Clock output. LVCMOS / LVTTL interface levels. TABLE 1. PIN DESCRIPTIONS Number 1, 6 2 3 4,7 5 8 Name VDDO VDD CLK GND nQ Q NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance VDD, VDDO = 3.465V VDD = 3.465V, VDDO = 2.625V 22 16 51 51 7 Test Conditions Minimum Typical Maximum 4 Units pF pF pF K K 8302AM-01 www.icst.com/products/hiperclocks.html 2 REV. A DECEMBER 10, 2002 Integrated Circuit Systems, Inc. ICS8302-01 LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Power Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 13 4 Units V V mA mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK CLK VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V 50 to VDDO/2 IOH = -100A 50 to VDDO/2 IOL = 100A -5 2.6 2.9 0.5 0.2 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 150 Units V V A A V V V V TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle 20% to 80% 133MHz 300 45 1.8 2.18 50 Test Conditions Minimum Typical Maximum 250 2.7 165 800 800 55 60 Units MHz ns ps ps ps % % tsk(o) tsk(pp) tR / tF odc 133MHz < 250MHz 40 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8302AM-01 www.icst.com/products/hiperclocks.html 3 REV. A DECEMBER 10, 2002 Integrated Circuit Systems, Inc. ICS8302-01 LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 13 4 Units V V mA mA TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol VDD VDDO IDD IDDO Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK CLK VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V 50 to VDDO/2 IOH = -100A 50 to VDDO/2 IOL = 100A -5 1.8 2.2 0.5 0.2 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 150 Units V V A A V V V V TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle 20% to 80% 133MHz 250 45 1.9 Test Conditions Minimum Typical Maximum 250 2.9 250 900 650 55 60 Units MHz ns ps ps ps % % tsk(o) tsk(pp) tR / tF odc 133MHz < 250MHz 40 NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8302AM-01 www.icst.com/products/hiperclocks.html 4 REV. A DECEMBER 10, 2002 Integrated Circuit Systems, Inc. ICS8302-01 LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT PARAMETER MEASUREMENT INFORMATION VDD, VDDO = 1.65V5% 2.05V5% 1.25V5% SCOPE LVCMOS Qx VDD VDDO SCOPE Qx LVCMOS GND = -1.65V5% GND = -1.25V5% 3.3V OUTPUT LOAD AC TEST CIRCUIT V 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT V Q DD CLK 2 V DDO DDO 2 V Q nQ V 2 DDO nQ DDO 2 2 t PD tsk(o) PROPAGATION DELAY PART 1 Q PART 2 Q nQ V V DD OUTPUT SKEW 2 V DDO 80% 80% 2 Clock Outputs DDO 20% t R 20% t F 2 tsk(pp) PART-TO-PART SKEW OUTPUT RISE/FALL TIME nQ VDDO VDDO 2 Q 2 t PW t PERIOD t PW t PERIOD odc = odc & tPERIOD 8302AM-01 www.icst.com/products/hiperclocks.html 5 REV. A DECEMBER 10, 2002 Integrated Circuit Systems, Inc. ICS8302-01 LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT RELIABILITY INFORMATION TABLE 5. JAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W 200 128.5C/W 103.3C/W 500 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8302-01 is: 322 8302AM-01 www.icst.com/products/hiperclocks.html 6 REV. A DECEMBER 10, 2002 Integrated Circuit Systems, Inc. ICS8302-01 LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT PACKAGE OUTLINE - SUFFIX M TABLE 6. PACKAGE DIMENSIONS SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM Reference Document: JEDEC Publication 95, MS-012 8302AM-01 www.icst.com/products/hiperclocks.html 7 REV. A DECEMBER 10, 2002 Integrated Circuit Systems, Inc. ICS8302-01 LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT Marking 8302A01 8302A01 Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature 0C to 70C 0C to 70C TABLE 7. ORDERING INFORMATION Part/Order Number ICS8302AM-01 ICS8302AM-01T While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8302AM-01 www.icst.com/products/hiperclocks.html 8 REV. A DECEMBER 10, 2002 |
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